Efficient threshold logic in 1T1R array

In-memory computing based on memristor logic is one of the most promising approaches to break ‘memory wall’ and ‘power wall’. However, some important logics (such as AND MAJ) cannot be implemented efficiently in 1T1R arrays, which makes it difficult design low-delay memristor-based systems. An efficient threshold proposed by adding an auxiliary MAGIC (N+1)-OR gate optimising driving voltage. The can completely a array without any additional resistor, achieve MAJ directly. Furthermore, 1-bit full adder logic, only requires three steps six memristors, designed. Our perform advantages terms area delay compared with previous designs.